FIG. 1 is a diagram showing a conventional full adder of the type shown in Japanese patent public disclosure No. 70636/1986. In this diagram, A denotes an augend signal; B is an inverse signal of an addend signal; C.sub.in a carry-in signal; TG.sub.1 to TG.sub.5 transmission gate circuits; INV.sub.1, INV.sub.2, INV.sub.3, INV.sub.4a and INV.sub.4b inverting amplifiers; GK.sub.1 a carry signal generating circuit; 1, 3, 5, 7 and 9 terminals; and 101 a signal line.
The augend signal A is applied to the terminal 1. The B of the addend signal is applied to the terminal 3. The carry-in signal C.sub.in is applied to the terminal 5. The augend signal A and the inverse signal B of the addend signal are supplied to a circuit consisting of the transmission gate circuits TG.sub.1 and TG.sub.2 and inverting amplifiers INV.sub.1 and INV.sub.2, so that an exclusive NOR (hereinafter, abbreviated to XNOR) is obtained. The XNOR signal of the augend signal A and the inverse signal B of the addend signal and the carry-in signal C.sub.in applied to the terminal 5 are supplied to a circuit consisting of the transmission gate circuits TG.sub.3 and TG.sub.4 and the inverting amplifiers INV.sub.3 and INV.sub.4a, so that an exclusive OR (hereinafter, abbreviated to XOR) is obtained. The XOR is provided as a sum signal S to the terminal 7. The carry-in signal C.sub.in is modified into the inverse signal by the inverting amplifier INV.sub.4b and is delivered to the transmission gate circuit TG.sub.5. The transmission gate circuit TG.sub.5 is controlled by the XNOR signal formed by the augend signal A and the inverse signal B of the addend signal, together with the inverse signal of the XNOR signal formed by the inverting amplifier INV.sub.3. When the gate circuit TG.sub.5 is closed, the carry signal is produced by the carry signal generating circuit GK.sub.1 in accordance with the augend signal A applied to the terminal 1 and the inverse signal B of the addend signal applied to the terminal 3. The inverse signal of the carry-in signal C.sub.in passing through the transmission gate circuit TG.sub.5, or the carry signal generated by the carry signal generating circuit GK.sub.1 is fed out to the terminal 9 as a carry-out signal CO.
Consideration is now given to the case where the sum signal S is changed, for example, as the inverse signal B of the addend signal applied to the terminal 3 changes, while the augend signal A and carry-in signal C.sub.in applied to the terminals 1 and 5, respectively remain constant.
The inverse signal B of the addend signal is applied to the inverting amplifier INV.sub.2 and inverted to become the addend signal B, and then the addend signal B and the inverse signal B of the addend signal are applied to two gate electrodes of the transmission gate circuits TG.sub.1 and TG.sub.2. Therefore, the change of the inverse signal B of the addend signal is delayed by the time required for it to pass through the inverting amplifier INV.sub.2, whereby the opening/closing operation of the transmission gate circuits TG.sub.1 and TG.sub.2 is also delayed at the same rate. The signal on the line 101 changes in response to the changes to the opened/closed state of the transmission gate circuits TG.sub.1 and TG.sub.2. The signal on the line 101 is applied to the inverting amplifier INV.sub.3 and inverted to become the inverse signal. This inverse signal and the signal on the line 101 are supplied to the gate electrodes of the transmission gate circuits TG.sub.3 and TG.sub.4. Thus, the change of the signal line 101 causes the change of the state of the transmission gate circuits TG.sub.3 and TG.sub.4 after the time delay allowed for passing through the inverting amplifier INV.sub.3. The sum signal S changes in response to the change of the states of the transmission gate circuits TG.sub.3 and TG.sub.4.
In the foregoing conventional full adder, the inverse signal is formed in itself. Therefore, there is a problem in that the time taken to produce the inverse signal causes a delay in the adding operation.